1. Field of the Invention
The present invention relates to a selective negative voltage word line decoder, particularly for Flash memory.
2. Description of the Related Art
More particularly, the present invention aims to provide an improvement of a decoder of the type described in application WO 02/41322 (FIGS. 5 and 6), allowing negative erase voltages to be selectively applied to word lines of a memory array, and thus page erasable Flash memories to be produced, one page representing one word line.
FIG. 1 very schematically represents a Flash memory array MA and a word line decoder WLDEC1 of the type described in the above-mentioned application. The memory array MA comprises floating-gate transistors FGT arranged in lines and in columns, each forming a non-volatile memory cell. The transistors FGT have their control gates linked to word lines WLi and their sources or their drains linked to bit lines BLk.
The decoder WLDEC1 comprises a predecoder PREDEC and a postdecoder POSTDEC powered by a voltage Vcc, supplying signals SELi for selecting word lines. When a determined address ADR is supplied to the decoder, the signal SELi for selecting the word line WLi designated by this address is set to 1 (voltage Vcc) while all the other selection signals are on 0 (ground). The signals SELi are applied to voltage adaptor circuits ADi each delivering a voltage Vi to a word line WLi. Each voltage adaptor ADi also receives a signal ERASE, a voltage VPOS and a voltage VNEG. The voltage Vi can be positive, negative or zero according to the operation being executed, the value of the selection signal SELi and the value of the voltages VPOS, VNEG.
As described by table 1 below, the signal ERASE is on 1 in the erase mode and on 0 in the other operating modes of the memory. The voltage VPOS is equal to a read voltage VREAD in the read mode, to a programming voltage VPP in the programming mode and to an erase inhibit voltage VEINHIB in the erase mode. The voltage VNEG is equal to a non-read voltage VNREAD in the read mode, to a programming inhibit voltage VPINHIB in the programming mode and to a negative erase voltage VER in the erase mode.
FIG. 2 represents the architecture of a voltage adaptor ADi. The adaptor ADi comprises a gate G1 of EXCLUSIVE OR type receiving the signals SELi and ERASE at input and delivering a signal COM. The signal COM is applied to an inverting gate G2 delivering a signal NCOM. The gates G1, G2 are powered by the voltage VPOS and the signals COM, NCOM are taken to the voltage VPOS when they are on 1. The signals COM and NCOM are applied to a driver stage 2 the output of which controls an inverting stage 3. The driver stage 2 comprises two branches in parallel each comprising a PMOS transistor in series with an NMOS transistor, respectively T0, T1 and T2, T3. The sources of the transistors T0 and T2 receive the voltage VPOS while the sources of the transistors T1 and T3 receive the voltage VNEG. The drain node of the transistors T2, T3 is connected to the gate of the transistor T1 and the drain node of the transistors T0, T1 is connected to the gate of the transistor T3. The inverting stage 3 comprises a PMOS transistor T4 in series with an NMOS transistor T5. The source of the transistor T4 receives the voltage VPOS and the source of the transistor T5 receives the voltage VNEG. The gates of the transistors T4, T5 are linked to the drain node of the transistors T2, T3, and the drain node of the transistors T4, T5 supplies the voltage Vi. The NMOS transistors T1, T3 and T5 are produced in a P-type well WP isolated from the substrate by an N-well, according to the known triple well technique.
The transfer function of the voltage adaptors ADi is described by table 1 below. In the page erase mode (ERASE=1) the voltage Vi applied to a word line WLi is equal to VER if the word line is selected (SELi=1) or to VEINHIB if the word line is not selected (SELi=0), the voltage VEINHIB here being equal to 4V. Outside periods of erasing, the voltage Vi applied to a selected word line WLi is equal to the voltage VPOS and the voltage Vi applied to a non-selected word line WLi (SELi=0) is zero.
TABLE 1ModeSELiERASECOMNCOMViRead0001Vi = VNEG = VNREAD = 0 V (GND)1010Vi = VPOS = VREAD = 4.5 VProgramming0001Vi = VNEG = VPINHIB = 0 V (GND)1010Vi = VPOS = VPP (8–10 V)Erase0110Vi = VPOS = VEINHIB (4 V)1101Vi = VNEG = VER (−8 V)
This negative voltage decoder, although being fully satisfactory per se, has the disadvantage that the voltage adaptors ADi, which form the terminating elements of the decoder, are of a relatively complex structure.
Now, with the developments in manufacturing methods of Flash memories, the technological pitch of the memories, that is the minimum distance between two word lines, is increasingly reduced. It thus becomes apparent that the surface of silicon available opposite each word line WLi becomes too small to allow voltage adaptors having the structure described above to be integrated.